用于超低电压∑-Δ变换器的130 nm CMOS全差分SC滤波器

D. Maljar, D. Arbet, V. Stopjaková
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引用次数: 0

摘要

本文介绍了超低电压Sigma-Delta模数转换器(∑-Δ ADC)的全差分(FD)开关电容(SC)积分器的设计和功能。该积分器设计用于差分输入信号,适用于标准130 nm CMOS技术下的超低电压∑-Δ ADC的主模拟模块。该积分器的主要模块是基于工作在亚阈值状态下的两级轨对轨(RtR) FD运算放大器(OPAMP)的运算跨导放大器(OTA)。该电路的特点是采用非标准OTA拓扑结构,采用SC共模反馈(CMFB)电路,并采用开关t门。所有这些子电路仅由0.6 V供电,实现增益24.09 dB和截止频率165.95 kHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
130 nm CMOS Fully Differential SC Filter for Ultra-Low Voltage ∑-Δ Converter
In this paper design and function of the fully differential (FD) switched-capacitor (SC) integrator for ultra-low voltage Sigma-Delta analog to digital converter (∑-Δ ADC) are presented. The proposed integrator was designed for differential input signal and applicable as a main analog block of ultra-low voltage ∑-Δ ADC in standard 130 nm CMOS technology. The main block of proposed integrator is operational transconductance amplifier (OTA) based on two-stage Rail-to-Rail (RtR) FD operational amplifier (OPAMP) working in sub-threshold regime. The characteristic properties of this circuit is non-standard OTA topology, using SC common-mode feedback (CMFB) circuit and using switching T-gates. All of these subcircuits are supplied by only 0.6 V with achieved gain 24.09 dB and cutoff frequency 165.95 kHz.
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