基于异构DNN加速器的节能计算

Md. Shazzad Hossain, I. Savidis
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引用次数: 1

摘要

基于深度神经网络(DNN)的加速器用于具有设备上智能的高能量约束边缘设备的探索正在研究界获得关注。尽管与cpu或gpu相比,定制加速器具有优越的整体性能和性能,但由于单片架构的范围有限,最先进的DNN加速器的能效和多功能性受到限制,整个加速器在任何给定时间只执行一个模型。本文提出了一种多电压域异构深度神经网络加速器结构,可同时执行具有不同功率性能工作点的多个模型。在65纳米CMOS技术下,通过SPICE仿真对所提出的架构和电路进行了评估。仿真结果表明,异质结构的能量效率提高到2.04 TOPS/W,而传统的单片和单电压域结构的能量效率为0.0458 TOPS/W。此外,当所有乘法累加(mac)单元工作在0.45 V电压下时,加速器SoC的总功耗降至1.34 W,而基线架构的功耗为3.72 W。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Energy Efficient Computing with Heterogeneous DNN Accelerators
The exploration of custom deep neural network (DNN) based accelerators for highly energy constrained edge devices with on-device intelligence is gaining traction in the research community. Despite the superior throughout and performance of custom accelerators as compared to CPUs or GPUs, the energy efficiency and versatility of state-of-the-art DNN accelerators is constrained due to the limited scope of monolithic architectures, where the entire accelerator executes only one model at any given time. In this paper, a multi-voltage domain heterogeneous DNN accelerator architecture is proposed that simultaneously executes multiple models with different power-performance operating points. The proposed architecture and circuits are evaluated with SPICE simulation in a 65 nm CMOS technology. The simulation results indicate that the proposed heterogeneous architecture improves the energy efficiency to 2.04 TOPS/W, while the conventional monolithic and single voltage domain architecture exhibits an energy efficiency of 0.0458 TOPS/W. In addition, the total power consumption of the accelerator SoC is reduced to 1.34 W as compared to the 3.72 W consumed by the baseline architecture when all multiply-and-accumulate (MACs) units operate at a voltage of 0.45 V.
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