在多问题处理器中,非阻塞负载、流缓冲区和推测执行有多有用?

K. Farkas, N. Jouppi, P. Chow
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引用次数: 72

摘要

我们研究了非阻塞负载、流缓冲区和推测执行分别使用和相互结合使用的相对性能影响。我们在静态调度的四问题处理器模型上模拟了SPEC92基准测试,运行来自Multiflow编译器的代码。非阻塞负载和流缓冲区都提供了显著的性能优势,它们的组合比单独使用要好得多。例如,使用64字节、2路集合关联缓存和32周期获取延迟,非阻塞负载将运行时间减少21%,而流缓冲区将运行时间减少26%,两者结合使用可减少47%。推测执行的增加进一步提高了我们所模拟的系统的性能,无论是否有非阻塞负载和流缓冲区,都能额外提高20%到40%。我们期望这三种技术的使用在未来几代微处理器中都很重要。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
How useful are non-blocking loads, stream buffers and speculative execution in multiple issue processors?
We investigate the relative performance impact of non-blocking loads, stream buffers, and speculative execution both used individually and in conjunction with each other. We have simulated the SPEC92 benchmarks on a statically scheduled quad-issue processor model, running code from the Multiflow compiler. Non-blocking loads and stream buffers both provide a significant performance advantage, and their combination performs significantly better than either alone. For example, with a 64-byte, 2-way set associative cache with 32 cycle fetch latency, non-blocking loads reduce the run-time by 21% while stream-buffers reduce it by 26%, and the combined use of the two yields a 47% reduction. The addition of speculative execution further improves the performance of the systems that we have simulated, with or without non-blocking loads and stream buffers, by an additional 20% to 4O%. We expect that the use of all three of these techniques will be important in future generations of microprocessors.<>
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