在fpga上实现晶体-二锂签名方案

Sara Ricci, L. Malina, P. Jedlicka, D. Smekal, J. Hajny, Peter Cíbik, P. Dobias
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引用次数: 32

摘要

2020年7月,基于晶格的晶体-锂数字签名方案被美国国家标准与技术研究院(NIST)选为后量子加密标准化过程的三个第三轮决赛入围者之一。在这项工作中,我们提出了用于现场可编程门阵列(fpga)的晶体-锂签名方案的第一个超高速集成电路硬件描述语言(VHDL)实现。由于我们基于并行的设计只需要少量的周期,在高频率下运行,并且在FPGA上使用合理数量的硬件资源,我们的实现每秒能够签署15832条消息,每秒验证10524个签名。其中签名算法在Virtex 7 UltraScale+ fpga上需要68461个查找表(lut)和86295个触发器(ff),验证算法需要61738个lut和34963个触发器。本文给出了每个安全级别的实验结果,并将我们基于vhdl的实现与相关的基于高级合成(High-Level Synthesis, HLS)的实现进行了比较。我们的解决方案大约要快114倍(在签名算法中),并且需要更少的硬件资源。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Implementing CRYSTALS-Dilithium Signature Scheme on FPGAs
In July 2020, the lattice-based CRYSTALS-Dilithium digital signature scheme has been chosen as one of the three third-round finalists in the post-quantum cryptography standardization process by the National Institute of Standards and Technology (NIST). In this work, we present the first Very High Speed Integrated Circuit Hardware Description Language (VHDL) implementation of the CRYSTALS-Dilithium signature scheme for Field-Programmable Gate Arrays (FPGAs). Due to our parallelization-based design requiring only low numbers of cycles, running at high frequency and using reasonable amount of hardware resources on FPGA, our implementation is able to sign 15832 messages per second and verify 10524 signatures per second. In particular, the signing algorithm requires 68461 Look-Up Tables (LUTs), 86295 Flip-Flops (FFs), and the verification algorithm takes 61738 LUTs and 34963 FFs on Virtex 7 UltraScale+ FPGAs. In this article, experimental results for each Dilithium security level are provided and our VHDL-based implementation is compared with related High-Level Synthesis (HLS)-based implementations. Our solution is ca 114 times faster (in the signing algorithm) and requires less hardware resources.
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