高水平低功耗FPGA设计方法

Proceedings of the IEEE 2000 National Aerospace and Electronics Conference. NAECON 2000. Engineering Tomorrow (Cat. No.00CH37093) Pub Date : 2000-10-10 DOI:10.1109/NAECON.2000.894960

F. Wolff, M. Knieser, D. Weyer, Chris Papachristou

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引用次数: 27

摘要

低功耗的高级设计很难实现，特别是FPGA设计。提出了一种设计技术，该技术使用预先计算的表来表征RTL和知识产权(IF)组件来估计功率。计算了实际表格，并演示了低功耗设计技术。结果表明，采用这种设计方法可以实现较低功耗的设计。

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High-level low power FPGA design methodology

High-level design for low power is difficult to accomplish especially for FPGA designs. Presents a design technique that uses pre-computed tables that characterize the RTL and Intellectual Property (IF) components to estimate power. Actual tables were computed and the low-power design technique demonstrated. The results show that a lower power design can be achieved given this design methodology.

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来源期刊

Proceedings of the IEEE 2000 National Aerospace and Electronics Conference. NAECON 2000. Engineering Tomorrow (Cat. No.00CH37093)

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