Design and Implementation of High Performance 2D Mesh NoC Based On New Proposed Router Using FPGA

The classic interconnection among Intellectual Property (IP) cores in a System on Chip (SoC) became ineffective due to the increase the numbers of processors on single chip. These factors lead to the emergence of Network on Chip (NoC) technology. In this paper, 2D Mesh network for 16 node were implemented with a new proposed router to solve packets conflict problem. This network has low resources, where the network utilization ratio of slices is about 24% from the available resources and the maximum frequency 102.093MHz. The total consumption power is about 150 mW for the network, where the consumption static power is 32 mW only. The router in this network has a schedule with a fixed priority, which leads to data flowing without any conflict among packets. Moreover, the crossbar in this router consists of one multiplexer, counter and without additional inputs buffers unlike traditional crossbar, which consists of five multiplexer with multiple input buffers. This router is implemented and tested on the FPGA Spartan 3A (XC3S700A) kit.