A new total static leakage estimation model for UDSM-based transistor stacks

This paper introduces a new input pattern dependent model for total static leakage estimation in ultra deep submicron processes. The model integrates gate tunnelling leakage, gate induced drain leakage (GIDL) and subthreshold leakage into a single leakage estimation framework. Subthreshold estimation is facilitated through the analytical estimation of nodal voltages between OFF transistors, while gate tunnelling leakage and GIDL are calculated based on simplified versions of their respective BSIM4 equations. The framework deals with all input patterns and accommodates scenarios where the various leakage currents interact. Similar approaches in the literature are either based on a look up table approach, and do not accommodate transistor stacks with varying widths, or are highly experimental and require a detailed knowledge of the transistor device physics. Several approaches also exist for modeling either subthreshold leakage or gate tunnelling leakage separately. Even those approaches use a lookup table approach, fix all widths in a transistor stack and/or limit the stack size to 2-3 transistors. The model proposed in this paper is tractable and almost completely analytical. It is capable of accommodating stacks with up to 4 transistors with varying transistor widths. A stack estimator function based on this model was coded in MatLab for the 65nm, 45nm and 32nm PTM process technologies. Compared with SPICE simulations the model exhibited an average error of 1.29%, 2.79%, 7.57% and 11.42% for stack sizes of 1, 2, 3 and 4 respectively across all three technologies. The model also exhibits significant runtime savings when compared with SPICE.