{"title":"基于存储单元的现场可编程VLSI处理器体系结构","authors":"Naotaka Ohsawa, M. Hariyama, M. Kameyama","doi":"10.1109/SICE.2002.1196603","DOIUrl":null,"url":null,"abstract":"This paper presents a field programmable VLSI based on a two-dimensional cell array and bit-serial architecture. Bit-serial architecture achieves high utilized ratio irrespective of the word length. Moreover, based on the regular data flow of bit-serial architecture, a lookup table implemented using a shift register is proposed for th cell. One of the arithmetic/logic, memory and control functions is selected in a cell. As a result, area of the cell is reduced.","PeriodicalId":301855,"journal":{"name":"Proceedings of the 41st SICE Annual Conference. SICE 2002.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Architecture of a field-programmable VLSI processor using memory-based cells\",\"authors\":\"Naotaka Ohsawa, M. Hariyama, M. Kameyama\",\"doi\":\"10.1109/SICE.2002.1196603\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a field programmable VLSI based on a two-dimensional cell array and bit-serial architecture. Bit-serial architecture achieves high utilized ratio irrespective of the word length. Moreover, based on the regular data flow of bit-serial architecture, a lookup table implemented using a shift register is proposed for th cell. One of the arithmetic/logic, memory and control functions is selected in a cell. As a result, area of the cell is reduced.\",\"PeriodicalId\":301855,\"journal\":{\"name\":\"Proceedings of the 41st SICE Annual Conference. SICE 2002.\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 41st SICE Annual Conference. SICE 2002.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SICE.2002.1196603\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 41st SICE Annual Conference. SICE 2002.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SICE.2002.1196603","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Architecture of a field-programmable VLSI processor using memory-based cells
This paper presents a field programmable VLSI based on a two-dimensional cell array and bit-serial architecture. Bit-serial architecture achieves high utilized ratio irrespective of the word length. Moreover, based on the regular data flow of bit-serial architecture, a lookup table implemented using a shift register is proposed for th cell. One of the arithmetic/logic, memory and control functions is selected in a cell. As a result, area of the cell is reduced.
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