Proposing a novel low-power high-speed mixed GDI Full Adder topology

This paper deals with the implementation of full adder chains by mixing different CMOS full adder topologies. The proposed approach is based on cascading fast Gate Diffusion Input (GDI) Full Adders interrupted by static gate having driving capability, such as inverter, thus exploiting the intrinsic low power consumption of such topologies. The results obtained show that the proposed mixed-topology approach based on GDI adders is capable of very low-power consumption and a very high-speed. This also enables a high degree of design freedom, given that the same (mixed) topology can be used for a wide range of applications. This greater flexibility also affords a significant reduction in the design effort. Delay and power has been evaluated by HSPICE simulation using TSMC 0.18µm CMOS technology considering minimum power design. The simulation results reveal better delay and power performance of proposed topology as compared to existing topologies at 1.8V supply voltage.