{"title":"采用RISC方法设计模糊处理器体系结构","authors":"H. Watanabe","doi":"10.1109/FUZZY.1992.258654","DOIUrl":null,"url":null,"abstract":"An attempt is made to design a fuzzy information processor as an application-specific processor using a quantitative approach. The approach was developed by reduced instruction set computer (RISC) architecture designers. The basic architecture proposed consists of a RISC as a core processor with special hardware functional units for fuzzy-logic-related operations. Fuzzy-related functional units should be either integrated into a core or placed as a coprocessor. In particular, the following two issues are considered: an instruction set for fuzzy information processing; and vector instruction for fuzzy theoretic operations.<<ETX>>","PeriodicalId":222263,"journal":{"name":"[1992 Proceedings] IEEE International Conference on Fuzzy Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"47","resultStr":"{\"title\":\"RISC approach to design of fuzzy processor architecture\",\"authors\":\"H. Watanabe\",\"doi\":\"10.1109/FUZZY.1992.258654\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An attempt is made to design a fuzzy information processor as an application-specific processor using a quantitative approach. The approach was developed by reduced instruction set computer (RISC) architecture designers. The basic architecture proposed consists of a RISC as a core processor with special hardware functional units for fuzzy-logic-related operations. Fuzzy-related functional units should be either integrated into a core or placed as a coprocessor. In particular, the following two issues are considered: an instruction set for fuzzy information processing; and vector instruction for fuzzy theoretic operations.<<ETX>>\",\"PeriodicalId\":222263,\"journal\":{\"name\":\"[1992 Proceedings] IEEE International Conference on Fuzzy Systems\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-03-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"47\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992 Proceedings] IEEE International Conference on Fuzzy Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FUZZY.1992.258654\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992 Proceedings] IEEE International Conference on Fuzzy Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FUZZY.1992.258654","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
RISC approach to design of fuzzy processor architecture
An attempt is made to design a fuzzy information processor as an application-specific processor using a quantitative approach. The approach was developed by reduced instruction set computer (RISC) architecture designers. The basic architecture proposed consists of a RISC as a core processor with special hardware functional units for fuzzy-logic-related operations. Fuzzy-related functional units should be either integrated into a core or placed as a coprocessor. In particular, the following two issues are considered: an instruction set for fuzzy information processing; and vector instruction for fuzzy theoretic operations.<>
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