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引用次数: 7
摘要
优化设计的FIR反馈DAC用于三阶单比特连续δ σ调制器，以降低功耗和抖动灵敏度。环路滤波器对FIR DAC增加的延迟进行了仔细的稳定。电流复用两级前馈补偿运放最大限度地减少了第一个积分器的电流消耗。采用0.18 μm CMOS技术设计的17位音频转换器的测量结果证明了我们技术的有效性。在24 kHz带宽下实现103 dB动态范围、102 dB a加权信噪比和106 dB SFDR, 1.8 V电源功耗280 μW。
A 280μW audio continuous-time ΔΣ modulator with 103dB DR and 102dB A-Weighted SNR
An optimally designed FIR feedback DAC is used in a third order, single bit continuous-time delta sigma modulator to reduce power dissipation and jitter sensitivity. The loop filter is carefully stabilized for the delay added by the FIR DAC. A current reuse two stage feedforward compensated opamp minimizes current consumption in the first integrator. The efficacy of our techniques is borne out by measurements from a 17 bit audio converter designed in a 0.18 μm CMOS technology. It achieves 103 dB dynamic range, 102 dB A-Weighted SNR and 106 dB SFDR in a 24 kHz bandwidth and dissipates 280 μW from a 1.8 V supply.
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