{"title":"实时通信系统的设计","authors":"O. Tanir, V. Agarwal, P. Bhatt","doi":"10.1109/RTA.1993.263115","DOIUrl":null,"url":null,"abstract":"The Design, Analysis and Synthesis Environment (DASE) has been developed to aid the designer in exploring the design space of telecommunication systems at the architectural level of design abstraction. DASE utilizes an internal representation called DSL (Design Specification Language) to capture the design intent and simulate, reconfigure and experiment with models using a DSL simulator. These features are supported through the use of an object-oriented library system capable of organizing models in a generic and re-useable form. Once the designer is satisfied with the architectural level design, the DSL models can be translated to synthesizeable behavioural VHDL code which can be used by lower level design automation tools. An example of the representation of a modular digital telecommunication switch element is given to demonstrate the modelling capabilities of DSL.<<ETX>>","PeriodicalId":293622,"journal":{"name":"[1993] Proceedings of the IEEE Workshop on Real-Time Applications","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"On the design of real-time telecommunication systems\",\"authors\":\"O. Tanir, V. Agarwal, P. Bhatt\",\"doi\":\"10.1109/RTA.1993.263115\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Design, Analysis and Synthesis Environment (DASE) has been developed to aid the designer in exploring the design space of telecommunication systems at the architectural level of design abstraction. DASE utilizes an internal representation called DSL (Design Specification Language) to capture the design intent and simulate, reconfigure and experiment with models using a DSL simulator. These features are supported through the use of an object-oriented library system capable of organizing models in a generic and re-useable form. Once the designer is satisfied with the architectural level design, the DSL models can be translated to synthesizeable behavioural VHDL code which can be used by lower level design automation tools. An example of the representation of a modular digital telecommunication switch element is given to demonstrate the modelling capabilities of DSL.<<ETX>>\",\"PeriodicalId\":293622,\"journal\":{\"name\":\"[1993] Proceedings of the IEEE Workshop on Real-Time Applications\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1993] Proceedings of the IEEE Workshop on Real-Time Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RTA.1993.263115\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1993] Proceedings of the IEEE Workshop on Real-Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTA.1993.263115","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On the design of real-time telecommunication systems
The Design, Analysis and Synthesis Environment (DASE) has been developed to aid the designer in exploring the design space of telecommunication systems at the architectural level of design abstraction. DASE utilizes an internal representation called DSL (Design Specification Language) to capture the design intent and simulate, reconfigure and experiment with models using a DSL simulator. These features are supported through the use of an object-oriented library system capable of organizing models in a generic and re-useable form. Once the designer is satisfied with the architectural level design, the DSL models can be translated to synthesizeable behavioural VHDL code which can be used by lower level design automation tools. An example of the representation of a modular digital telecommunication switch element is given to demonstrate the modelling capabilities of DSL.<>