神经网络硬件性能标准

E. V. Keulen, S. Colak, H. Withagen, Hans Hegt
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引用次数: 19

摘要

如今,许多现实世界的问题都需要快速处理的神经网络来实时解决。因此,硬件实现变得必不可少。接下来的问题是为特定的应用选择合适的芯片。为此,需要一套合适的硬件性能标准来比较神经网络芯片的性能。最重要的标准与网络在给定精度下处理信息的速度有关。为此提出了一个新的判据。“有效连接位数”代表芯片的有效精度。“每秒(有效)连接原语”标准现在提供了一个新的速度标准,该标准标准化为在连接中处理的信息值的数量。除此之外,我们还提出了另一个称为“可重构数”的新标准,作为衡量芯片可重构性和尺寸的标准。与现有的传统标准(如“每秒连接数”)相比,使用这些标准可以更中性地看待神经网络芯片的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Neural network hardware performance criteria
Nowadays, many real world problems need fast processing neural networks to come up with a solution in real time. Therefore hardware implementation becomes indispensable. The problem is then to choose the right chip that is to be used for a particular application. For this, a proper set of hardware performance criteria is needed to be able to compare the performance of neural network chips. The most important criterion is related to the speed a network processes information with a given accuracy. For this a new criterion is proposed. The 'effective number of connection bits' represents the effective accuracy of a chip. The '(effective) connection primitives per second' criterion now provides a new speed criterion normalized to the amount of information value that is processed in a connection. In addition to this we also propose another new criterion called 'reconfigurability number' as a measure for the reconfigurability and size of a chip. Using these criteria gives a much more neutral view of the performance of a neural network chip than the existing conventional criteria, such as 'connections per second'.<>
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