{"title":"多核架构下多核执行的性能分析和新模型","authors":"Pedro Valero-Lara, F. Pelayo","doi":"10.1109/ICCI-CC.2013.6622243","DOIUrl":null,"url":null,"abstract":"Nowadays, due to massively parallel characteristics of current many-core architectures, these devices are not only being used in order to exploit data-parallelism and to minimize the execution time in a single problem, but, they are beginning to be used in order both to execute and to increase the performances when executing more than one application simultaneously. In this work, we provide a performance analysis on the use of current many-core architectures for this new purpose; this performance analysis has been carried out over two different many-core architectures. Furthermore, two different programming approaches to tackle this new role have been tested. The results so obtained show that a increase in the computational requirements implies an important fall in performance. The main objective of this paper is to explain the reasons for this behavior, and afterwards, to propose a set of alternatives to deal with these disadvantages previously mentioned.","PeriodicalId":130244,"journal":{"name":"2013 IEEE 12th International Conference on Cognitive Informatics and Cognitive Computing","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Analysis in performance and new model for multiple kernels executions on many-core architectures\",\"authors\":\"Pedro Valero-Lara, F. Pelayo\",\"doi\":\"10.1109/ICCI-CC.2013.6622243\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Nowadays, due to massively parallel characteristics of current many-core architectures, these devices are not only being used in order to exploit data-parallelism and to minimize the execution time in a single problem, but, they are beginning to be used in order both to execute and to increase the performances when executing more than one application simultaneously. In this work, we provide a performance analysis on the use of current many-core architectures for this new purpose; this performance analysis has been carried out over two different many-core architectures. Furthermore, two different programming approaches to tackle this new role have been tested. The results so obtained show that a increase in the computational requirements implies an important fall in performance. The main objective of this paper is to explain the reasons for this behavior, and afterwards, to propose a set of alternatives to deal with these disadvantages previously mentioned.\",\"PeriodicalId\":130244,\"journal\":{\"name\":\"2013 IEEE 12th International Conference on Cognitive Informatics and Cognitive Computing\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-07-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE 12th International Conference on Cognitive Informatics and Cognitive Computing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCI-CC.2013.6622243\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 12th International Conference on Cognitive Informatics and Cognitive Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCI-CC.2013.6622243","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis in performance and new model for multiple kernels executions on many-core architectures
Nowadays, due to massively parallel characteristics of current many-core architectures, these devices are not only being used in order to exploit data-parallelism and to minimize the execution time in a single problem, but, they are beginning to be used in order both to execute and to increase the performances when executing more than one application simultaneously. In this work, we provide a performance analysis on the use of current many-core architectures for this new purpose; this performance analysis has been carried out over two different many-core architectures. Furthermore, two different programming approaches to tackle this new role have been tested. The results so obtained show that a increase in the computational requirements implies an important fall in performance. The main objective of this paper is to explain the reasons for this behavior, and afterwards, to propose a set of alternatives to deal with these disadvantages previously mentioned.