{"title":"TX-0是一种具有256 * 256存储器的晶体管计算机","authors":"J. Mitchell, K. Olsen","doi":"10.1145/1455533.1455556","DOIUrl":null,"url":null,"abstract":"Synopsis: TX-0 is a high-speed digital computer which was built at Lincoln Laboratory to demonstrate and operationally test 5-megapulse transistor circuitry and a 65,536-word magnetic-core memory. The word length is 19 bits; 1 bit is a parity check bit for memory, 16 bits are assigned to memory addressing, and the 2 remaining bits are used to select among three memory-reference instructions and one microprogramming instruction. The logic is performed by standardized packages using surface barrier transistors. Fig. 1 shows TX-0 with the arithmetic element just beyond the console and the memory on the far left. Part I of this paper covers the TX-0 memory, and Part II the TX-0 circuitry.","PeriodicalId":259150,"journal":{"name":"AIEE-IRE '56 (Eastern)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1956-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"TX-0, a transistor computer with a 256 by 256 memory\",\"authors\":\"J. Mitchell, K. Olsen\",\"doi\":\"10.1145/1455533.1455556\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Synopsis: TX-0 is a high-speed digital computer which was built at Lincoln Laboratory to demonstrate and operationally test 5-megapulse transistor circuitry and a 65,536-word magnetic-core memory. The word length is 19 bits; 1 bit is a parity check bit for memory, 16 bits are assigned to memory addressing, and the 2 remaining bits are used to select among three memory-reference instructions and one microprogramming instruction. The logic is performed by standardized packages using surface barrier transistors. Fig. 1 shows TX-0 with the arithmetic element just beyond the console and the memory on the far left. Part I of this paper covers the TX-0 memory, and Part II the TX-0 circuitry.\",\"PeriodicalId\":259150,\"journal\":{\"name\":\"AIEE-IRE '56 (Eastern)\",\"volume\":\"117 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1956-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AIEE-IRE '56 (Eastern)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1455533.1455556\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AIEE-IRE '56 (Eastern)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1455533.1455556","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
TX-0, a transistor computer with a 256 by 256 memory
Synopsis: TX-0 is a high-speed digital computer which was built at Lincoln Laboratory to demonstrate and operationally test 5-megapulse transistor circuitry and a 65,536-word magnetic-core memory. The word length is 19 bits; 1 bit is a parity check bit for memory, 16 bits are assigned to memory addressing, and the 2 remaining bits are used to select among three memory-reference instructions and one microprogramming instruction. The logic is performed by standardized packages using surface barrier transistors. Fig. 1 shows TX-0 with the arithmetic element just beyond the console and the memory on the far left. Part I of this paper covers the TX-0 memory, and Part II the TX-0 circuitry.