A parametrized algorithm that implements sequential, causal, and cache memory consistency

Presents an algorithm that implements cache coherence which can be used to implement sequential, causal or cache consistency in distributed shared memory (DSM) systems. For this purpose, it has a parameter that allows one to choose the consistency model to be implemented. In our algorithm, when implementing causal and cache consistency, all read and write operations are executed locally (i.e. they are fast). It is known that no sequential algorithm has only fast memory operations. However, in our algorithm, when implementing sequential consistency, all write operations and some read operations are fast. The algorithm uses propagation and full replication, where values written by a process are propagated to the rest of processes. This works in a cyclic-turn fashion, with each process of the DSM system broadcasting one message in turn. The values written by the process are sent within the message (instead of sending one message for each write operation), but unnecessary values are excluded. All this allows one to control the amount of message traffic due to the algorithm.