FPGA Implementation using Novel Co-Design Approach of Real-Time Speech Chaos based Crypto-Watermarking Prototype

This paper presents a two Nexys FPGAs implementation of a Least Significant Bit (LSB) watermarking applied on real-time speech signals over a serial communication system. The watermarking technique has been strengthened by means of a chaos-based encryption scheme for the used watermark image. The speech acquisition is performed using FPGA inbuilt microphone while the recovery has been realized through a loudspeaker as output device for the watermarked signal and VGA monitor for the watermark image respectively. The transmission of the watermarked signal has been implemented using Universal Asynchronous Receiver Transmitter (UART) serial protocol between two FPGA boards. The LSB IP-Cores developed and integrated in the watermarking prototype have been synthesized by means of a co-design approach using Vivado-HLS. The realized prototype has required performances of 1132 LUT area using a speed of 130 Mhz and a power consumption of no more than 159 mW. Lastly, good results have been obtained of watermarking imperceptibility and security with low robustness performances against signal processing and geometric cryptanalysis attacks.