{"title":"SoC -前面的路","authors":"M. Mehendale","doi":"10.1109/VLSID.2006.149","DOIUrl":null,"url":null,"abstract":"Summary form only for tutorial. System-on-a-chip is an evolving definition where a current generation system implemented with multiple chips on a board translates to a system-on-a-chip for the next generation. This is enabled by advances in the semiconductor technology which support increasing levels of single chip integration. For system components which can be efficiently implemented in CMOS, integrating them on a single chip (SoC) offers the most optimal solution in terms of die size, unit cost, form factor, power, performance and reliability. The SoC development process however implies longer cycle time and high NRE costs. This makes SoCs economically viable only for high volume, high NR applications. The increasing complexity of the systems coupled with the technology scaling challenges have significant negative impact on both the cycle time and the NRE costs. The SoC design challenge in business terms is then to improve execution efficiency at a rate faster than the complexity increase, so as to increase the TAM serviced by SoCs. This talk covers the system and technology trends, highlight their implications and discuss directions to address the ever increasing SoC design challenge.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"SoC - The Road Ahead\",\"authors\":\"M. Mehendale\",\"doi\":\"10.1109/VLSID.2006.149\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only for tutorial. System-on-a-chip is an evolving definition where a current generation system implemented with multiple chips on a board translates to a system-on-a-chip for the next generation. This is enabled by advances in the semiconductor technology which support increasing levels of single chip integration. For system components which can be efficiently implemented in CMOS, integrating them on a single chip (SoC) offers the most optimal solution in terms of die size, unit cost, form factor, power, performance and reliability. The SoC development process however implies longer cycle time and high NRE costs. This makes SoCs economically viable only for high volume, high NR applications. The increasing complexity of the systems coupled with the technology scaling challenges have significant negative impact on both the cycle time and the NRE costs. The SoC design challenge in business terms is then to improve execution efficiency at a rate faster than the complexity increase, so as to increase the TAM serviced by SoCs. This talk covers the system and technology trends, highlight their implications and discuss directions to address the ever increasing SoC design challenge.\",\"PeriodicalId\":382435,\"journal\":{\"name\":\"VLSI design (Print)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-01-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI design (Print)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSID.2006.149\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI design (Print)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2006.149","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Summary form only for tutorial. System-on-a-chip is an evolving definition where a current generation system implemented with multiple chips on a board translates to a system-on-a-chip for the next generation. This is enabled by advances in the semiconductor technology which support increasing levels of single chip integration. For system components which can be efficiently implemented in CMOS, integrating them on a single chip (SoC) offers the most optimal solution in terms of die size, unit cost, form factor, power, performance and reliability. The SoC development process however implies longer cycle time and high NRE costs. This makes SoCs economically viable only for high volume, high NR applications. The increasing complexity of the systems coupled with the technology scaling challenges have significant negative impact on both the cycle time and the NRE costs. The SoC design challenge in business terms is then to improve execution efficiency at a rate faster than the complexity increase, so as to increase the TAM serviced by SoCs. This talk covers the system and technology trends, highlight their implications and discuss directions to address the ever increasing SoC design challenge.