Power Optimized Low Pass Digital FIR Filter Using Five Modular Redundancy and Parallel Adding Methods

The development of fault-tolerant filtering is crucial to the dependability of any communication network or digital signal processors system. FIR filtering with simultaneous error correcting algorithms have been developed, which increase the system's redundancy and complexity. Design and implementation of a power-optimized low pass digital FIR filter based on the ripple carry adder and the radix 4 modified booth algorithm are presented in this work, as well as use of the Five Modular Redundancy (FMR) approach. This paper aims to apply the parallel adding method (PAM) is used and the radix 4 modified booth algorithm on low pass digital FIR filter and Five Modular Redundancy (FMR) method is used to correct the error in transmitted signals and compare the existing low pass digital FIR filter. These filtering utilised error correcting codes with the forward error - correcting ability, resulting in enhanced chip space and fault - tolerant. The recommended methodology employs less redundancy module than previous techniques and decreases the size of such filtering by around 21.18 percent, decreases the cost of systems development by nearly the same proportion. Our method is written in Verilog, and it is implemented on a Vivado Basys 3 board from Xilinx. The Xilinx vivado 2021.1 tool is used to calculate the following parameters: area, power, delay, and LUT. This paper discusses the synthesis as well as the outcomes.