通过二值化硬件加速深度学习

Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, M. Ikebe, T. Asai, M. Motomura
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引用次数: 4

摘要

面向硬件加速深度神经网络处理的方法对于各种嵌入式智能应用非常重要。本文综述了近年来在高效神经网络处理方面的研究成果。重点研究了能量和面积效率高的神经网络处理器的二值化方法。本文首先提出了一种采用内存处理架构的高效二值化深度神经网络处理器。与之前的产品相比,真正的处理器LSI实现了高性能和高能效。然后,我们提出了一种基于FPGA的二值化神经网络处理器的架构探索技术。研究结果表明,二值化后的硬件可以同时利用多种不同的并行性,从而获得很高的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Accelerating deep learning by binarized hardware
Hardware-oriented approaches to accelerate deep neural network processing are very important for various embedded intelligent applications. This paper is a summary of our recent achievements for efficient neural network processing. We focus on the binarization approach for energy- and area-efficient neural network processor. We first present an energy-efficient binarized processor for deep neural networks by employing inmemory processing architecture. The real processor LSI achieves high performance and energy-efficiency compared to prior works. We then present an architecture exploration technique for binarized neural network processor on an FPGA. The exploration result indicates that the binarized hardware achieves very high performance by exploiting multiple different parallelisms at the same time.
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