低温MOSFET技术,具有肖特基势垒源/漏极、高k栅极电介质和金属栅极电极

Shiyang Zhu, H. Yu, S. Whang, J.H. Chen, C. Shen, Chunxiang Zhu, S.J. Lee, M. Li, D. Chan, W. Yoo, A. Du, C. Tung, J. Singh, A. Chin, D. Kwong
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引用次数: 0

摘要

在本文中,我们使用低温工艺演示了具有CVD HfO/sub - 2/高k介电介质,PVD HfN/TaN金属栅极和PtSi(用于PMOS)和DySi/sub - 2-x/(用于NMOS)硅化物源/漏的块状ssdt(肖特基势垒S/D)。在形成高k栅堆后,在420/spl℃的最高温度下进行表面去除、清洗、浸镀和硅化处理1h。该过程可以很容易地扩展到UTB-SOI结构。P-SSDT具有优异的电学性能,如空穴迁移率和S/D串联电阻。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectrics and metal gate electrode
In this paper, we demonstrate a bulk SSDTs (Schottky barrier S/D) with CVD HfO/sub 2/ high-k dielectric, PVD HfN/TaN metal gate and PtSi (for PMOS) and DySi/sub 2-x/ (for NMOS) silicide source/drain using a low temperature process. Surface removing, cleaning, dipping and silicidation processes are carried out at highest temperature of 420/spl deg/C for 1h after a high-k gate stack formation. The process can be easily extended to UTB-SOI structures. The P-SSDT shows a excellent electrical properties like hole mobility and S/D series resistance.
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