Shiyang Zhu, H. Yu, S. Whang, J.H. Chen, C. Shen, Chunxiang Zhu, S.J. Lee, M. Li, D. Chan, W. Yoo, A. Du, C. Tung, J. Singh, A. Chin, D. Kwong
{"title":"低温MOSFET技术,具有肖特基势垒源/漏极、高k栅极电介质和金属栅极电极","authors":"Shiyang Zhu, H. Yu, S. Whang, J.H. Chen, C. Shen, Chunxiang Zhu, S.J. Lee, M. Li, D. Chan, W. Yoo, A. Du, C. Tung, J. Singh, A. Chin, D. Kwong","doi":"10.1109/ISDRS.2003.1272085","DOIUrl":null,"url":null,"abstract":"In this paper, we demonstrate a bulk SSDTs (Schottky barrier S/D) with CVD HfO/sub 2/ high-k dielectric, PVD HfN/TaN metal gate and PtSi (for PMOS) and DySi/sub 2-x/ (for NMOS) silicide source/drain using a low temperature process. Surface removing, cleaning, dipping and silicidation processes are carried out at highest temperature of 420/spl deg/C for 1h after a high-k gate stack formation. The process can be easily extended to UTB-SOI structures. The P-SSDT shows a excellent electrical properties like hole mobility and S/D series resistance.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectrics and metal gate electrode\",\"authors\":\"Shiyang Zhu, H. Yu, S. Whang, J.H. Chen, C. Shen, Chunxiang Zhu, S.J. Lee, M. Li, D. Chan, W. Yoo, A. Du, C. Tung, J. Singh, A. Chin, D. Kwong\",\"doi\":\"10.1109/ISDRS.2003.1272085\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we demonstrate a bulk SSDTs (Schottky barrier S/D) with CVD HfO/sub 2/ high-k dielectric, PVD HfN/TaN metal gate and PtSi (for PMOS) and DySi/sub 2-x/ (for NMOS) silicide source/drain using a low temperature process. Surface removing, cleaning, dipping and silicidation processes are carried out at highest temperature of 420/spl deg/C for 1h after a high-k gate stack formation. The process can be easily extended to UTB-SOI structures. The P-SSDT shows a excellent electrical properties like hole mobility and S/D series resistance.\",\"PeriodicalId\":369241,\"journal\":{\"name\":\"International Semiconductor Device Research Symposium, 2003\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Semiconductor Device Research Symposium, 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISDRS.2003.1272085\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Semiconductor Device Research Symposium, 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISDRS.2003.1272085","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectrics and metal gate electrode
In this paper, we demonstrate a bulk SSDTs (Schottky barrier S/D) with CVD HfO/sub 2/ high-k dielectric, PVD HfN/TaN metal gate and PtSi (for PMOS) and DySi/sub 2-x/ (for NMOS) silicide source/drain using a low temperature process. Surface removing, cleaning, dipping and silicidation processes are carried out at highest temperature of 420/spl deg/C for 1h after a high-k gate stack formation. The process can be easily extended to UTB-SOI structures. The P-SSDT shows a excellent electrical properties like hole mobility and S/D series resistance.