{"title":"内置自重新配置系统的容错网格连接的处理器阵列直接备件更换","authors":"I. Takanami","doi":"10.1109/DFTVS.2001.966762","DOIUrl":null,"url":null,"abstract":"Gives built-in self-reconfiguring systems for mesh-connected processor arrays with faulty processors (PEs) which are directly replaced by spare PEs on two orthogonal lines at the edges of the arrays or on the diagonal line of the arrays. To do so, using a Hopfield-type neural network model, we present an algorithm for reconstructing the arrays mentioned above and show its efficiency of reconstruction by computer simulations. Next, we show how the algorithm can be realized by a digital neural circuit. The circuit can be embedded in a target processor array to reconstruct quickly the array with faulty PEs without the aid of a host computer. This implies that the proposed systems are effective in enhancing the run-time reliabilities of the processor arrays.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Built-in self-reconfiguring systems for fault tolerant mesh-connected processor arrays by direct spare replacement\",\"authors\":\"I. Takanami\",\"doi\":\"10.1109/DFTVS.2001.966762\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Gives built-in self-reconfiguring systems for mesh-connected processor arrays with faulty processors (PEs) which are directly replaced by spare PEs on two orthogonal lines at the edges of the arrays or on the diagonal line of the arrays. To do so, using a Hopfield-type neural network model, we present an algorithm for reconstructing the arrays mentioned above and show its efficiency of reconstruction by computer simulations. Next, we show how the algorithm can be realized by a digital neural circuit. The circuit can be embedded in a target processor array to reconstruct quickly the array with faulty PEs without the aid of a host computer. This implies that the proposed systems are effective in enhancing the run-time reliabilities of the processor arrays.\",\"PeriodicalId\":187031,\"journal\":{\"name\":\"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.2001.966762\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.2001.966762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Built-in self-reconfiguring systems for fault tolerant mesh-connected processor arrays by direct spare replacement
Gives built-in self-reconfiguring systems for mesh-connected processor arrays with faulty processors (PEs) which are directly replaced by spare PEs on two orthogonal lines at the edges of the arrays or on the diagonal line of the arrays. To do so, using a Hopfield-type neural network model, we present an algorithm for reconstructing the arrays mentioned above and show its efficiency of reconstruction by computer simulations. Next, we show how the algorithm can be realized by a digital neural circuit. The circuit can be embedded in a target processor array to reconstruct quickly the array with faulty PEs without the aid of a host computer. This implies that the proposed systems are effective in enhancing the run-time reliabilities of the processor arrays.