G. Fischer, D. Martynenko, O. Klymenko, S. Olonbayar, D. Kreiser, J. Digel, M. Masini, M. Grozing, R. Kraemer
{"title":"IR-UWB单片收发器,用于高频段操作,符合IEEE 802.15.a","authors":"G. Fischer, D. Martynenko, O. Klymenko, S. Olonbayar, D. Kreiser, J. Digel, M. Masini, M. Grozing, R. Kraemer","doi":"10.1109/ICUWB.2013.6663861","DOIUrl":null,"url":null,"abstract":"This paper describes a monolithic integrated single-chip transceiver intended for impulse radio (IR) - Ultra-wide Band (UWB) applications compliant to the IEEE 802.15.4a standard. The transceiver operates in the higher UWB band on the mandatory channel #9 (7.9872 GHz). The implemented nominal data rate is 850 kb/sec. The presented chip consists of the entire RF-front-end, 6-bit-resolution successive approximation register (SAR) analogue-to-digital converter (ADC), and the baseband processor running with a clock of 31.2 MHz. The analogue frontend can be further segmented into a pulse generation and transmit part and a quadrature direct down conversion receiver part, whereas both parts share a frequency synthesizer based on an integer-N phase-locked loop (PLL). The impulse generation is based on the gated oscillator principle allowing required on-off keying (OOK) as well as binary phase shift keying (BPSK). While the receiver supports both, coherent and non-coherent impulse detection, here only non-coherent operation will be presented. The baseband processor part contains a separated 499.2 MHz clocked block for transmitter control and provides a serial peripheral interface (SPI) for data exchange with an external micro controller. The presented chip was fabricated in a 0.25 μm SiGe:C BiCMOS technology occupying a Si area of 3.25 - 3.25 mm2.","PeriodicalId":159159,"journal":{"name":"2013 IEEE International Conference on Ultra-Wideband (ICUWB)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"IR-UWB single-chip transceiver for high-band operation compliant to IEEE 802.15.4a\",\"authors\":\"G. Fischer, D. Martynenko, O. Klymenko, S. Olonbayar, D. Kreiser, J. Digel, M. Masini, M. Grozing, R. Kraemer\",\"doi\":\"10.1109/ICUWB.2013.6663861\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a monolithic integrated single-chip transceiver intended for impulse radio (IR) - Ultra-wide Band (UWB) applications compliant to the IEEE 802.15.4a standard. The transceiver operates in the higher UWB band on the mandatory channel #9 (7.9872 GHz). The implemented nominal data rate is 850 kb/sec. The presented chip consists of the entire RF-front-end, 6-bit-resolution successive approximation register (SAR) analogue-to-digital converter (ADC), and the baseband processor running with a clock of 31.2 MHz. The analogue frontend can be further segmented into a pulse generation and transmit part and a quadrature direct down conversion receiver part, whereas both parts share a frequency synthesizer based on an integer-N phase-locked loop (PLL). The impulse generation is based on the gated oscillator principle allowing required on-off keying (OOK) as well as binary phase shift keying (BPSK). While the receiver supports both, coherent and non-coherent impulse detection, here only non-coherent operation will be presented. The baseband processor part contains a separated 499.2 MHz clocked block for transmitter control and provides a serial peripheral interface (SPI) for data exchange with an external micro controller. The presented chip was fabricated in a 0.25 μm SiGe:C BiCMOS technology occupying a Si area of 3.25 - 3.25 mm2.\",\"PeriodicalId\":159159,\"journal\":{\"name\":\"2013 IEEE International Conference on Ultra-Wideband (ICUWB)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Conference on Ultra-Wideband (ICUWB)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICUWB.2013.6663861\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference on Ultra-Wideband (ICUWB)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICUWB.2013.6663861","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
IR-UWB single-chip transceiver for high-band operation compliant to IEEE 802.15.4a
This paper describes a monolithic integrated single-chip transceiver intended for impulse radio (IR) - Ultra-wide Band (UWB) applications compliant to the IEEE 802.15.4a standard. The transceiver operates in the higher UWB band on the mandatory channel #9 (7.9872 GHz). The implemented nominal data rate is 850 kb/sec. The presented chip consists of the entire RF-front-end, 6-bit-resolution successive approximation register (SAR) analogue-to-digital converter (ADC), and the baseband processor running with a clock of 31.2 MHz. The analogue frontend can be further segmented into a pulse generation and transmit part and a quadrature direct down conversion receiver part, whereas both parts share a frequency synthesizer based on an integer-N phase-locked loop (PLL). The impulse generation is based on the gated oscillator principle allowing required on-off keying (OOK) as well as binary phase shift keying (BPSK). While the receiver supports both, coherent and non-coherent impulse detection, here only non-coherent operation will be presented. The baseband processor part contains a separated 499.2 MHz clocked block for transmitter control and provides a serial peripheral interface (SPI) for data exchange with an external micro controller. The presented chip was fabricated in a 0.25 μm SiGe:C BiCMOS technology occupying a Si area of 3.25 - 3.25 mm2.