{"title":"利用Silvaco制备90nm NMOS晶体管的优化","authors":"M. Muhamad, Sunaily Lokman, H. Hussin","doi":"10.1109/SCORED.2009.5443057","DOIUrl":null,"url":null,"abstract":"In this paper, a 90 nm NMOS was designed and fabricate to study its electrical characteristics. ATHENA and ATLAS module of SILVACO software are the tools used in simulating the electrical performance of the transistor. The parameters under investigation were the VTH, Id-Vg and Id-Vd relationship. From the simulation result, it was shown that the gate oxide thickness, channel doping, VTH adjust implant and the dosage of halo implantation were contribute in determining the VTH value and Id-Vg curve. From the simulation result, optimum solution is found in which VTH value of 0.2685 is achieved. The value is in line with ITRS guideline for 90 nm device.","PeriodicalId":443287,"journal":{"name":"2009 IEEE Student Conference on Research and Development (SCOReD)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Optimization in fabricating 90nm NMOS transistors using Silvaco\",\"authors\":\"M. Muhamad, Sunaily Lokman, H. Hussin\",\"doi\":\"10.1109/SCORED.2009.5443057\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a 90 nm NMOS was designed and fabricate to study its electrical characteristics. ATHENA and ATLAS module of SILVACO software are the tools used in simulating the electrical performance of the transistor. The parameters under investigation were the VTH, Id-Vg and Id-Vd relationship. From the simulation result, it was shown that the gate oxide thickness, channel doping, VTH adjust implant and the dosage of halo implantation were contribute in determining the VTH value and Id-Vg curve. From the simulation result, optimum solution is found in which VTH value of 0.2685 is achieved. The value is in line with ITRS guideline for 90 nm device.\",\"PeriodicalId\":443287,\"journal\":{\"name\":\"2009 IEEE Student Conference on Research and Development (SCOReD)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Student Conference on Research and Development (SCOReD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SCORED.2009.5443057\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Student Conference on Research and Development (SCOReD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCORED.2009.5443057","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimization in fabricating 90nm NMOS transistors using Silvaco
In this paper, a 90 nm NMOS was designed and fabricate to study its electrical characteristics. ATHENA and ATLAS module of SILVACO software are the tools used in simulating the electrical performance of the transistor. The parameters under investigation were the VTH, Id-Vg and Id-Vd relationship. From the simulation result, it was shown that the gate oxide thickness, channel doping, VTH adjust implant and the dosage of halo implantation were contribute in determining the VTH value and Id-Vg curve. From the simulation result, optimum solution is found in which VTH value of 0.2685 is achieved. The value is in line with ITRS guideline for 90 nm device.
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