一个用于对VHDL属性进行宏时间和微时间建模的框架

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410686

Mohamed Belhadj, R. McConnell, P. Guernic

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引用次数: 7

摘要

本文使用一种正式定义的语言，介绍了VHDL的一些重要构造的正式定义。同时使用宏观时间和微观时间尺度。包括微时间，或时间delta，允许作者描述变量以及信号。为了便于说明，他们给出了VHDL的信号属性。这项工作代表了VHDL完全翻译成正式验证语言SIGNAL的前奏。SIGNAL可以为验证VHDL程序提供基础。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A framework for macro- and micro-time to model VHDL attributes

The work presented introduces a formal definition of some important constructs of VHDL, using a formally defined language. Both macro time and micro time scales are used. The inclusion of micro time, or time deltas, allows the authors to describe variables as well as signals. For the purpose of illustration they present the signal attributes of VHDL. This work represents a prelude to the complete translation of VHDL into the formal verification language SIGNAL. SIGNAL can then provide a basis for verifying VHDL programs.<>

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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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