MOS数字单元的布局合成

27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI:10.1109/DAC.1990.114861

A. Domic

{"title":"MOS数字单元的布局合成","authors":"A. Domic","doi":"10.1109/DAC.1990.114861","DOIUrl":null,"url":null,"abstract":"The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Layout synthesis of MOS digital cells\",\"authors\":\"A. Domic\",\"doi\":\"10.1109/DAC.1990.114861\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed.<<ETX>>\",\"PeriodicalId\":118552,\"journal\":{\"name\":\"27th ACM/IEEE Design Automation Conference\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"27th ACM/IEEE Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1990.114861\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1990.114861","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

综述了MOS数字电路单元生成的主要问题。讨论集中在直接使用任意单元，或快速生成新的库项，而不是应用一般的位置和路径算法。具体来说，讨论了布尔门的晶体管排序、单元路由和多边形生成。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Layout synthesis of MOS digital cells

The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

27th ACM/IEEE Design Automation Conference

自引率

0.00%

发文量