Adiabatic Flip-Flop and SRAM Design for an Adiabatic Reversible Microprocessor

Adiabatic reversible computing is a well-developed implementation for future energy-efficient computing that reduces heat generation by introducing a tradeoff between energy and speed. By using reversible logic and switching the circuits slowly, relative to their RC time constants, energy can be recovered, and dissipation can be dramatically reduced. Adiabatic microprocessors contain a large number of sequential elements, such as flip-flops and SRAM cells, that generally do not lend themselves to energy recovery. In this paper we present the design of an adiabatic flip-flop and an adiabatic SRAM cell that perform energy recovery. The adiabatic flip-flop performs partial energy recovery by combining a reversible master latch and an irreversible follower latch. The adiabatic SRAM cell performs energy recovery before new data is written by adding select transistors into the power lines of the cell. These proposed sequential elements are designed in 90 nm technology and their simulations prove to have a lower energy dissipation than their CMOS counterpart. A 16-bit MIPS reversible microprocessor is presented demonstrating the large-scale integration of both the adiabatic flip-flop and the adiabatic SRAM proposed in this work.