采用折叠三圈变压器和65nm CMOS双前馈技术的28ghz紧凑LNAs,具有1.9 dB NF

Xiangrong Huang, Haikun Jia, W. Deng, Zhihua Wang, B. Chi
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引用次数: 1

摘要

本文介绍了两种用于毫米波相控阵的ka波段低噪声放大器。为了提高LNA的噪声性能,减小芯片面积,提出了折叠三圈变压器和电磁双前馈技术。第一个两级单端LNA由一个共门(CG)输入级和一个共源(CS)输出级组成,实现1.9 dB最小噪声系数(NF), 16.7 dB峰值增益,4.3 GHz 3db带宽(BW)从25.6到29.9 GHz, -12 dBm输入1db增益压缩点(IP1dB), 13.2 mW Pdc。第二个LNA采用电流复用拓扑,以0.6 dB的NF衰减为代价,将功耗降低到3.6 mW。所提出的LNAs已在65nm CMOS工艺中制备。两个lna的核心芯片面积相同,为200µm × 300µm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
28 GHz Compact LNAs with 1.9 dB NF Using Folded Three-Coil Transformer and Dual-Feedforward Techniques in 65nm CMOS
This article presents two Ka-band low-noise amplifiers (LNA) for millimeter-wave (mm-wave) phased-arrays. The folded three-coil transformer and EM dual-feedforward techniques are proposed to improve the LNA's noise performance and reduce the chip area. The first two-stage single-ended LNA, consisting of a common-gate (CG) input stage and a common-source (CS) output stage, achieves 1.9 dB minimum noise figure (NF), 16.7 dB peak gain, 4.3 GHz 3-dB bandwidth (BW) from 25.6 to 29.9 GHz, and -12 dBm input 1-dB gain-compression-point (IP1dB) with 13.2 mW Pdc. The second LNA employs the current-reuse topology, which reduces the power consumption to 3.6 mW at the cost of a 0.6 dB NF degradation. The proposed LNAs have been fabricated in 65nm CMOS process. The two LNAs have the same 200 µm × 300 µm core chip area.
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