Xiangrong Huang, Haikun Jia, W. Deng, Zhihua Wang, B. Chi
{"title":"采用折叠三圈变压器和65nm CMOS双前馈技术的28ghz紧凑LNAs,具有1.9 dB NF","authors":"Xiangrong Huang, Haikun Jia, W. Deng, Zhihua Wang, B. Chi","doi":"10.1109/RFIC54546.2022.9863182","DOIUrl":null,"url":null,"abstract":"This article presents two Ka-band low-noise amplifiers (LNA) for millimeter-wave (mm-wave) phased-arrays. The folded three-coil transformer and EM dual-feedforward techniques are proposed to improve the LNA's noise performance and reduce the chip area. The first two-stage single-ended LNA, consisting of a common-gate (CG) input stage and a common-source (CS) output stage, achieves 1.9 dB minimum noise figure (NF), 16.7 dB peak gain, 4.3 GHz 3-dB bandwidth (BW) from 25.6 to 29.9 GHz, and -12 dBm input 1-dB gain-compression-point (IP1dB) with 13.2 mW Pdc. The second LNA employs the current-reuse topology, which reduces the power consumption to 3.6 mW at the cost of a 0.6 dB NF degradation. The proposed LNAs have been fabricated in 65nm CMOS process. The two LNAs have the same 200 µm × 300 µm core chip area.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"28 GHz Compact LNAs with 1.9 dB NF Using Folded Three-Coil Transformer and Dual-Feedforward Techniques in 65nm CMOS\",\"authors\":\"Xiangrong Huang, Haikun Jia, W. Deng, Zhihua Wang, B. Chi\",\"doi\":\"10.1109/RFIC54546.2022.9863182\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents two Ka-band low-noise amplifiers (LNA) for millimeter-wave (mm-wave) phased-arrays. The folded three-coil transformer and EM dual-feedforward techniques are proposed to improve the LNA's noise performance and reduce the chip area. The first two-stage single-ended LNA, consisting of a common-gate (CG) input stage and a common-source (CS) output stage, achieves 1.9 dB minimum noise figure (NF), 16.7 dB peak gain, 4.3 GHz 3-dB bandwidth (BW) from 25.6 to 29.9 GHz, and -12 dBm input 1-dB gain-compression-point (IP1dB) with 13.2 mW Pdc. The second LNA employs the current-reuse topology, which reduces the power consumption to 3.6 mW at the cost of a 0.6 dB NF degradation. The proposed LNAs have been fabricated in 65nm CMOS process. The two LNAs have the same 200 µm × 300 µm core chip area.\",\"PeriodicalId\":415294,\"journal\":{\"name\":\"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC54546.2022.9863182\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC54546.2022.9863182","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
28 GHz Compact LNAs with 1.9 dB NF Using Folded Three-Coil Transformer and Dual-Feedforward Techniques in 65nm CMOS
This article presents two Ka-band low-noise amplifiers (LNA) for millimeter-wave (mm-wave) phased-arrays. The folded three-coil transformer and EM dual-feedforward techniques are proposed to improve the LNA's noise performance and reduce the chip area. The first two-stage single-ended LNA, consisting of a common-gate (CG) input stage and a common-source (CS) output stage, achieves 1.9 dB minimum noise figure (NF), 16.7 dB peak gain, 4.3 GHz 3-dB bandwidth (BW) from 25.6 to 29.9 GHz, and -12 dBm input 1-dB gain-compression-point (IP1dB) with 13.2 mW Pdc. The second LNA employs the current-reuse topology, which reduces the power consumption to 3.6 mW at the cost of a 0.6 dB NF degradation. The proposed LNAs have been fabricated in 65nm CMOS process. The two LNAs have the same 200 µm × 300 µm core chip area.