{"title":"基于温控伪电阻的纳米安培面积高效电流基准","authors":"Italo Bruni, F. Olivera, A. Petraglia","doi":"10.1109/CAE56623.2023.10087014","DOIUrl":null,"url":null,"abstract":"This paper proposes a CMOS current reference circuit that avoids the use of huge area resistors. In order to achieve an independent-of-absolute-temperature (IOAT) current, proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages are respectively applied to the drain and gate terminals of a n-MOS pseudo-resistor. The circuit was carried out using a 180 nm CMOS process. Extensive post-layout simulation results in Spectre show that the proposed topology presents a current consumption of 6.30 nA (typical), a temperature coefficient (TC) of 219 ppm/°C in a range from −40 to 120 °C, and a line regulation (LR) of 12.08 %. The proposed current reference occupies a silicon area of 0.0018 mm2.","PeriodicalId":212534,"journal":{"name":"2023 Argentine Conference on Electronics (CAE)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Nano-Ampere Area-Efficient Current Reference Based on Temperature-Controlled Pseudo-Resistor\",\"authors\":\"Italo Bruni, F. Olivera, A. Petraglia\",\"doi\":\"10.1109/CAE56623.2023.10087014\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a CMOS current reference circuit that avoids the use of huge area resistors. In order to achieve an independent-of-absolute-temperature (IOAT) current, proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages are respectively applied to the drain and gate terminals of a n-MOS pseudo-resistor. The circuit was carried out using a 180 nm CMOS process. Extensive post-layout simulation results in Spectre show that the proposed topology presents a current consumption of 6.30 nA (typical), a temperature coefficient (TC) of 219 ppm/°C in a range from −40 to 120 °C, and a line regulation (LR) of 12.08 %. The proposed current reference occupies a silicon area of 0.0018 mm2.\",\"PeriodicalId\":212534,\"journal\":{\"name\":\"2023 Argentine Conference on Electronics (CAE)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-03-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 Argentine Conference on Electronics (CAE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CAE56623.2023.10087014\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 Argentine Conference on Electronics (CAE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAE56623.2023.10087014","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Nano-Ampere Area-Efficient Current Reference Based on Temperature-Controlled Pseudo-Resistor
This paper proposes a CMOS current reference circuit that avoids the use of huge area resistors. In order to achieve an independent-of-absolute-temperature (IOAT) current, proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages are respectively applied to the drain and gate terminals of a n-MOS pseudo-resistor. The circuit was carried out using a 180 nm CMOS process. Extensive post-layout simulation results in Spectre show that the proposed topology presents a current consumption of 6.30 nA (typical), a temperature coefficient (TC) of 219 ppm/°C in a range from −40 to 120 °C, and a line regulation (LR) of 12.08 %. The proposed current reference occupies a silicon area of 0.0018 mm2.