{"title":"用于大规模并行分布式内存MIMD计算机的编译器","authors":"G. Sabot","doi":"10.1109/FMPC.1992.234910","DOIUrl":null,"url":null,"abstract":"The author describes the techniques that are used by the CM Compiler Engine to map the fine-grained array parallelism of languages such as Fortan 90 and C onto the Connection Machine (CM) architectures. The same compiler is used for node-level programming of the CM-5, for global programming of the CM-5, and for global programming of the SIMD (single-instruction multiple-data) CM-2. A new compiler phase is used to generate two classes of output code: code for a scalar control processor, which executes SPARC assembler, and code aimed at a model of the CM-5's parallel-processing elements. The model is embodied in a new RISC (reduced instruction set computer)-like vector instruction set called PEAC. The control program distributes parallel data at runtime among the processor nodes of the target machine. Each of these nodes is itself superpipelined and superscalar. An innovative scheduler overlaps the execution of multiple PEAC operations, while conventional vector processing techniques keep the pipelines filled.<<ETX>>","PeriodicalId":117789,"journal":{"name":"[Proceedings 1992] The Fourth Symposium on the Frontiers of Massively Parallel Computation","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1992-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"A compiler for a massively parallel distributed memory MIMD computer\",\"authors\":\"G. Sabot\",\"doi\":\"10.1109/FMPC.1992.234910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The author describes the techniques that are used by the CM Compiler Engine to map the fine-grained array parallelism of languages such as Fortan 90 and C onto the Connection Machine (CM) architectures. The same compiler is used for node-level programming of the CM-5, for global programming of the CM-5, and for global programming of the SIMD (single-instruction multiple-data) CM-2. A new compiler phase is used to generate two classes of output code: code for a scalar control processor, which executes SPARC assembler, and code aimed at a model of the CM-5's parallel-processing elements. The model is embodied in a new RISC (reduced instruction set computer)-like vector instruction set called PEAC. The control program distributes parallel data at runtime among the processor nodes of the target machine. Each of these nodes is itself superpipelined and superscalar. An innovative scheduler overlaps the execution of multiple PEAC operations, while conventional vector processing techniques keep the pipelines filled.<<ETX>>\",\"PeriodicalId\":117789,\"journal\":{\"name\":\"[Proceedings 1992] The Fourth Symposium on the Frontiers of Massively Parallel Computation\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings 1992] The Fourth Symposium on the Frontiers of Massively Parallel Computation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FMPC.1992.234910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings 1992] The Fourth Symposium on the Frontiers of Massively Parallel Computation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FMPC.1992.234910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A compiler for a massively parallel distributed memory MIMD computer
The author describes the techniques that are used by the CM Compiler Engine to map the fine-grained array parallelism of languages such as Fortan 90 and C onto the Connection Machine (CM) architectures. The same compiler is used for node-level programming of the CM-5, for global programming of the CM-5, and for global programming of the SIMD (single-instruction multiple-data) CM-2. A new compiler phase is used to generate two classes of output code: code for a scalar control processor, which executes SPARC assembler, and code aimed at a model of the CM-5's parallel-processing elements. The model is embodied in a new RISC (reduced instruction set computer)-like vector instruction set called PEAC. The control program distributes parallel data at runtime among the processor nodes of the target machine. Each of these nodes is itself superpipelined and superscalar. An innovative scheduler overlaps the execution of multiple PEAC operations, while conventional vector processing techniques keep the pipelines filled.<>
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