用于10位5-Msamples/Sec流水线ADC的伪反转采样保持电路设计

2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems Pub Date : 2009-12-01 DOI:10.1109/ELECTRO.2009.5441162

M. Santosh, K. C. Behera, S. Bose

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引用次数: 0

摘要

本文介绍了一种用于10位、5毫秒采样/秒的流水线ADC的伪反转采样保持电路的设计。采样保持电路采用0.35µm奥地利微系统技术，以1 KHz, 1.2 Vp-p的正弦输入和5 MHz的采样时钟进行仿真。仿真结果表明，最坏情况下采样误差为1mV，信噪比为60dB。样品保持电路的布局面积为0.007mm2，功耗为1.7 mW。

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Design of pseudo flip-around sample hold- circuit for 10-bit, 5-Msamples/Sec pipeline ADC

This paper describes the design of a pseudo flip-around sample- hold circuit for a 10-bit, 5-Msamples/sec pipeline ADC. The sample-hold circuit is simulated in 0.35 µm Austria Microsystems technology with a 1 KHz, 1.2 Vp-p sinusoidal input and a sampling clock of 5 MHz. The simulation shows a worst case sampling error of 1mV, SNR of 60dB. The layout of the sample hold circuit occupies an area of 0.007mm2 and consumes 1.7 mW of power.

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2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems

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