The future of electrical I/O for microprocessors

High-speed CMOS microprocessor I/O has scaled aggressively over the past decade in terms of power and performance largely due to advances in equalization and clocking techniques. With future multi-core processors expected to require ≫1TB/s bandwidth and dramatically improved power efficiency, there has been some question as to whether electrical I/O will continue to satisfy chip-to-chip communication requirements over the next decade. In this paper, we show that electrical signaling has the power, performance, and density scaling potential to enable the next several generations of systems and applications. Circuit innovation is aggressively pushing link power efficiency toward 1–2mW/Gb/s while departures from legacy channels to include new topologies and materials can significantly improve the power/performance/density tradeoff. Statistical link-level design tools that allow designers to rapidly quantify high-level architecture tradeoffs will enable balanced link designs that co-optimize power, performance, and channel topology.