三维集成电路中TSV信号完整性建模与测量

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI:10.1109/ASPDAC.2013.6509551

Joohee Kim, Joungho Kim

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引用次数: 12

摘要

为了保证基于tsv的通道在3D IC设计中的信号完整性，对基于tsv的通道进行了建模和测量，包括tsv和rdl，具有各种性能指标，如插入损耗、噪声耦合和眼图。在对制造的TSV通道进行建模和测量的基础上，提出了通道信号完整性的设计准则。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Signal integrity modeling and measurement of TSV in 3D IC

In order to guarantee signal integrity of a TSV-based channel in 3D IC design, the modeling and measurements are conducted for electrical characterization of the TSV-based channel including TSVs and RDLs with various performance metrics such as insertion loss, noise coupling and eye diagrams. Based on the modeling and measurements of the fabricated TSV channels, design guide for the signal integrity of the channel is proposed.

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来源期刊

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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