一种用于模式识别的高效形态联想记忆硬件实现

E. Guzman Ramirez, S. Alvarado, M. A. Ramírez, Luis Rosario
{"title":"一种用于模式识别的高效形态联想记忆硬件实现","authors":"E. Guzman Ramirez, S. Alvarado, M. A. Ramírez, Luis Rosario","doi":"10.1109/CERMA.2010.58","DOIUrl":null,"url":null,"abstract":"This work describes a hardware architecture implementation of the morphological associative memories (MAM) using reconfigurable hardware devices such as FPGA (Field Programmable Gates Arrays) and its applications in pattern recognition systems. Both learning and recognition processes of the MAM are implemented by means of a parallel architecture using VHSIC Hardware Description Language, obtaining high speed of processing. The performance of the modeled architecture was evaluated when Morphological Hetero associative Memories (MHM) in both max and min types are used. Our proposal was tested to signal recognitions, for this purpose, it was necessary to implement an acquisition and memory systems.","PeriodicalId":119218,"journal":{"name":"2010 IEEE Electronics, Robotics and Automotive Mechanics Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Efficient Morphological Associative Memories Hardware Implementation for Pattern Recognition Applications\",\"authors\":\"E. Guzman Ramirez, S. Alvarado, M. A. Ramírez, Luis Rosario\",\"doi\":\"10.1109/CERMA.2010.58\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work describes a hardware architecture implementation of the morphological associative memories (MAM) using reconfigurable hardware devices such as FPGA (Field Programmable Gates Arrays) and its applications in pattern recognition systems. Both learning and recognition processes of the MAM are implemented by means of a parallel architecture using VHSIC Hardware Description Language, obtaining high speed of processing. The performance of the modeled architecture was evaluated when Morphological Hetero associative Memories (MHM) in both max and min types are used. Our proposal was tested to signal recognitions, for this purpose, it was necessary to implement an acquisition and memory systems.\",\"PeriodicalId\":119218,\"journal\":{\"name\":\"2010 IEEE Electronics, Robotics and Automotive Mechanics Conference\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-09-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE Electronics, Robotics and Automotive Mechanics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CERMA.2010.58\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Electronics, Robotics and Automotive Mechanics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CERMA.2010.58","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本工作描述了一种使用可重构硬件设备(如FPGA(现场可编程门阵列))实现形态联想记忆(MAM)的硬件架构及其在模式识别系统中的应用。MAM的学习和识别过程采用VHSIC硬件描述语言并行架构实现,处理速度快。在形态学异联想记忆(MHM)的最大和最小类型下,对模型的性能进行了评价。我们的建议进行了信号识别测试,为此,有必要实现一个采集和记忆系统。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Efficient Morphological Associative Memories Hardware Implementation for Pattern Recognition Applications
This work describes a hardware architecture implementation of the morphological associative memories (MAM) using reconfigurable hardware devices such as FPGA (Field Programmable Gates Arrays) and its applications in pattern recognition systems. Both learning and recognition processes of the MAM are implemented by means of a parallel architecture using VHSIC Hardware Description Language, obtaining high speed of processing. The performance of the modeled architecture was evaluated when Morphological Hetero associative Memories (MHM) in both max and min types are used. Our proposal was tested to signal recognitions, for this purpose, it was necessary to implement an acquisition and memory systems.
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