A systolic array architecture for morphological operators using arbitrary structuring elements

This paper presents an 2-D systolic array architecture for an efficient implementation of gray-scale morphological dilation using arbitrary structuring element and used it to design 2-stage pipelined architecture for morphological opening. The proposed systolic array architecture processes pixels on stream that eliminates the need for buffering image data prior to processing. Additionally, unlike existing systolic array architecture, it does not necessarily adds delay element for processing pixels of an image thereby increasing the processing frame rate. The 2-stage pipelined architecture, on the other hand, provides better performance compared to naive hardware implementation to compute morphological opening. The architecture has been synthesized using Xilinx Design Suite 14.2 ISE and prototyped on Virtex 6 FPGA Board (XC6VLX240T-3FF1156) and verified using Xilinx ISIM Simulator. The architecture provides real time performance when tested for high resolution images using moderate size non-rectangular SEs and results outperforms existing systolic array implementation.