用于下一代VLSI架构的集值逻辑电路

Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138) Pub Date : 1998-05-27 DOI:10.1109/ISMVL.1998.679324

T. Aoki, T. Higuchi

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引用次数: 2

摘要

本文提出了“集值逻辑”的概念，作为下一代集成系统免于互连问题的基础。集值逻辑系统采用可复用的信息载体，以减少互连，实现高度并行处理。本文还提出了一种利用伪随机序列作为信息载体构建集值逻辑vlsi的新方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Set-valued logic circuits for next generation VLSI architectures

This paper presents the concept of "set-valued logic" as a foundation for next-generation integrated systems free from interconnection problems. The set-valued logic system employs multiplexable information carriers to achieve highly parallel processing with reduced interconnections. This paper also proposes a new approach to the construction of set-valued logic VLSIs employing pseudo-random sequences as information carriers.

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Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)

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