{"title":"高清图像处理器协同验证的模块化套件","authors":"M. Bertola, R. Irvine","doi":"10.1109/ESTMED.2007.4375817","DOIUrl":null,"url":null,"abstract":"High-end image processors are complex hardware and software systems. The verification of such devices poses a number of problems during the different phases of their life cycle. This paper proposes a modular verification suite that reuses the same test cases at every stage of the system's life cycle. It uses models of increasing fidelity with a common set of verification tools to provide consistent verification coverage. Because of the feedback that can be provided by its modular design, the suite improves continuously and can be used to increase the verification coverage for future designs.","PeriodicalId":428196,"journal":{"name":"2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia","volume":"1 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Modular Suite for High-Definition Image Processor Co-Verification\",\"authors\":\"M. Bertola, R. Irvine\",\"doi\":\"10.1109/ESTMED.2007.4375817\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-end image processors are complex hardware and software systems. The verification of such devices poses a number of problems during the different phases of their life cycle. This paper proposes a modular verification suite that reuses the same test cases at every stage of the system's life cycle. It uses models of increasing fidelity with a common set of verification tools to provide consistent verification coverage. Because of the feedback that can be provided by its modular design, the suite improves continuously and can be used to increase the verification coverage for future designs.\",\"PeriodicalId\":428196,\"journal\":{\"name\":\"2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia\",\"volume\":\"1 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESTMED.2007.4375817\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESTMED.2007.4375817","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Modular Suite for High-Definition Image Processor Co-Verification
High-end image processors are complex hardware and software systems. The verification of such devices poses a number of problems during the different phases of their life cycle. This paper proposes a modular verification suite that reuses the same test cases at every stage of the system's life cycle. It uses models of increasing fidelity with a common set of verification tools to provide consistent verification coverage. Because of the feedback that can be provided by its modular design, the suite improves continuously and can be used to increase the verification coverage for future designs.