{"title":"细胞合成基准","authors":"D. Hill, B. Preas","doi":"10.1109/DAC.1990.114873","DOIUrl":null,"url":null,"abstract":"Cell synthesis is the process of transforming detailed, transistor level specifications and technology information into layout. While cell synthesis has been investigated for several years, only recently has it become practical and pervasive. To accelerate this process and to encourage further refinement, a set of benchmarks was developed for cell synthesis tools. The benchmarks try to balance the objective of universal participation against that of comprehensive testing. They cover the areas of arithmetic, finite state machines (FSM), RAM, and analog design and include detailed descriptions of technology rules. Discussed are the benchmarks, and how they may be used as a guide to future work in this field.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"289 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Benchmarks for cell synthesis\",\"authors\":\"D. Hill, B. Preas\",\"doi\":\"10.1109/DAC.1990.114873\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cell synthesis is the process of transforming detailed, transistor level specifications and technology information into layout. While cell synthesis has been investigated for several years, only recently has it become practical and pervasive. To accelerate this process and to encourage further refinement, a set of benchmarks was developed for cell synthesis tools. The benchmarks try to balance the objective of universal participation against that of comprehensive testing. They cover the areas of arithmetic, finite state machines (FSM), RAM, and analog design and include detailed descriptions of technology rules. Discussed are the benchmarks, and how they may be used as a guide to future work in this field.<<ETX>>\",\"PeriodicalId\":118552,\"journal\":{\"name\":\"27th ACM/IEEE Design Automation Conference\",\"volume\":\"289 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"27th ACM/IEEE Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1990.114873\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1990.114873","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Cell synthesis is the process of transforming detailed, transistor level specifications and technology information into layout. While cell synthesis has been investigated for several years, only recently has it become practical and pervasive. To accelerate this process and to encourage further refinement, a set of benchmarks was developed for cell synthesis tools. The benchmarks try to balance the objective of universal participation against that of comprehensive testing. They cover the areas of arithmetic, finite state machines (FSM), RAM, and analog design and include detailed descriptions of technology rules. Discussed are the benchmarks, and how they may be used as a guide to future work in this field.<>