FPL演示:SERVE:敏捷硬件开发平台与云IDE和云fpga

2022 32nd International Conference on Field-Programmable Logic and Applications (FPL) Pub Date : 2022-08-01 DOI:10.1109/FPL57034.2022.00087

Zelin Wang, Ke Zhang, Yisong Chang, Yanlong Yin, Yuxiao Chen, Ran Zhao, Songyue Wang, Mingyu Chen, Yungang Bao

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引用次数: 1

摘要

我们介绍了一个用于敏捷硬件软件协同设计的云平台SERVE，它集成了云IDE和云fpga。SERVE使用户能够专注于逻辑设计，而无需面对设置FPGA工具和开发环境的麻烦。用户可以在云IDE中编写和模拟硬件逻辑，然后通过持续集成(CI)管道生成比特流文件。最后，将位流文件部署在FPGA板上。将执行大量的测试台架以确保硬件逻辑的正确性。我们将演示修改RISC- V处理器的工作流程，并使用SERVE快速评估设计更改。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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FPL Demo: SERVE: Agile Hardware Development Platform with Cloud IDE and Cloud FPGAs

We introduce SERVE, a cloud platform for agile hardware software co-design, with cloud IDE and cloud FPGAs integrated. SERVE enables users to focus on logic designs, without facing the hassle of setting up FPGA tools and development environment. Users can write and simulate hardware logic in the cloud IDE and then generate bitstream files through a Continuous Integration (CI) pipeline. Finally, the bitstream files are deployed on an FPGA board. A great amount of testbenches will be executed to ensure the correctness of the hardware logic. We will demo a workflow of modifying a RISC- V processor and getting the design change quickly evaluated using SERVE.

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2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)

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