{"title":"基于fpga的高效硬件实现计算密集型算法的设计方法和优化技术综述","authors":"Syed Manzoor Qasim, S. A. Abbasi, B. Almashary","doi":"10.1109/MSPCT.2009.5164238","DOIUrl":null,"url":null,"abstract":"Field programmable gate arrays (FPGAs) have emerged as platform of choice for efficient hardware realization of computation intensive algorithms because of their intrinsic parallelism and flexible architecture. However, to achieve high performance, FPGA must be supported by efficient design methodology and optimization techniques. In this paper, FPGA-based design methodology and optimization techniques that can be employed to obtain area, speed and power efficient circuits are reviewed and presented.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A review of FPGA-based design methodology and optimization techniques for efficient hardware realization of computation intensive algorithms\",\"authors\":\"Syed Manzoor Qasim, S. A. Abbasi, B. Almashary\",\"doi\":\"10.1109/MSPCT.2009.5164238\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Field programmable gate arrays (FPGAs) have emerged as platform of choice for efficient hardware realization of computation intensive algorithms because of their intrinsic parallelism and flexible architecture. However, to achieve high performance, FPGA must be supported by efficient design methodology and optimization techniques. In this paper, FPGA-based design methodology and optimization techniques that can be employed to obtain area, speed and power efficient circuits are reviewed and presented.\",\"PeriodicalId\":179541,\"journal\":{\"name\":\"2009 International Multimedia, Signal Processing and Communication Technologies\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-03-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Multimedia, Signal Processing and Communication Technologies\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MSPCT.2009.5164238\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Multimedia, Signal Processing and Communication Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MSPCT.2009.5164238","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A review of FPGA-based design methodology and optimization techniques for efficient hardware realization of computation intensive algorithms
Field programmable gate arrays (FPGAs) have emerged as platform of choice for efficient hardware realization of computation intensive algorithms because of their intrinsic parallelism and flexible architecture. However, to achieve high performance, FPGA must be supported by efficient design methodology and optimization techniques. In this paper, FPGA-based design methodology and optimization techniques that can be employed to obtain area, speed and power efficient circuits are reviewed and presented.