{"title":"采用无源电感的CMOS功率放大器的设计方法","authors":"M. Božanić, S. Sinha","doi":"10.1109/AFRCON.2007.4401587","DOIUrl":null,"url":null,"abstract":"This paper presents the design methodology of an integrated power amplifier (PA), and coins the methodology as a software routine: for a given set of PA specifications, CMOS process parameters, the routine computes the passive component values for a Class-E based PA. The routine includes the matching network for standard impedance loads. The program also provides its user with a spiral inductor calculator, which can be used to determine inductance and parasitic values for an integrated square planar spiral inductor. The same tool has the ability to extract SPICE (tSPICE) netlist of inductor geometry, which can be used in the post-layout simulations of the PA. Operation of the program was demonstrated by simulations in AMS 0.35 mum single-supply process for a 10 dBm, 2.4 GHz PA design.","PeriodicalId":112129,"journal":{"name":"AFRICON 2007","volume":"237 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Design methodology for a CMOS based power amplifier deploying a passive inductor\",\"authors\":\"M. Božanić, S. Sinha\",\"doi\":\"10.1109/AFRCON.2007.4401587\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design methodology of an integrated power amplifier (PA), and coins the methodology as a software routine: for a given set of PA specifications, CMOS process parameters, the routine computes the passive component values for a Class-E based PA. The routine includes the matching network for standard impedance loads. The program also provides its user with a spiral inductor calculator, which can be used to determine inductance and parasitic values for an integrated square planar spiral inductor. The same tool has the ability to extract SPICE (tSPICE) netlist of inductor geometry, which can be used in the post-layout simulations of the PA. Operation of the program was demonstrated by simulations in AMS 0.35 mum single-supply process for a 10 dBm, 2.4 GHz PA design.\",\"PeriodicalId\":112129,\"journal\":{\"name\":\"AFRICON 2007\",\"volume\":\"237 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AFRICON 2007\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AFRCON.2007.4401587\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AFRICON 2007","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AFRCON.2007.4401587","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design methodology for a CMOS based power amplifier deploying a passive inductor
This paper presents the design methodology of an integrated power amplifier (PA), and coins the methodology as a software routine: for a given set of PA specifications, CMOS process parameters, the routine computes the passive component values for a Class-E based PA. The routine includes the matching network for standard impedance loads. The program also provides its user with a spiral inductor calculator, which can be used to determine inductance and parasitic values for an integrated square planar spiral inductor. The same tool has the ability to extract SPICE (tSPICE) netlist of inductor geometry, which can be used in the post-layout simulations of the PA. Operation of the program was demonstrated by simulations in AMS 0.35 mum single-supply process for a 10 dBm, 2.4 GHz PA design.
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