{"title":"利用FPGA技术有效地实现了一维DCT","authors":"H. El-Banna, A. El-Fattah, W. Fakhr","doi":"10.1109/ECBS.2004.1316719","DOIUrl":null,"url":null,"abstract":"This paper describes and represents different algorithms and efficient implementation of one-dimensional 8 point discrete cosine transform on field programmable gate arrays. One of the main objectives is to minimize the complexity of operations as much as possible while maintaining low delays and high-speed throughput. Distributed arithmetic is a powerful technique that has been used for fast and efficient implementation of 1D DCT on FPGA.","PeriodicalId":137219,"journal":{"name":"Proceedings. 11th IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, 2004.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"An efficient implementation of the 1D DCT using FPGA technology\",\"authors\":\"H. El-Banna, A. El-Fattah, W. Fakhr\",\"doi\":\"10.1109/ECBS.2004.1316719\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes and represents different algorithms and efficient implementation of one-dimensional 8 point discrete cosine transform on field programmable gate arrays. One of the main objectives is to minimize the complexity of operations as much as possible while maintaining low delays and high-speed throughput. Distributed arithmetic is a powerful technique that has been used for fast and efficient implementation of 1D DCT on FPGA.\",\"PeriodicalId\":137219,\"journal\":{\"name\":\"Proceedings. 11th IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, 2004.\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-05-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 11th IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECBS.2004.1316719\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 11th IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECBS.2004.1316719","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An efficient implementation of the 1D DCT using FPGA technology
This paper describes and represents different algorithms and efficient implementation of one-dimensional 8 point discrete cosine transform on field programmable gate arrays. One of the main objectives is to minimize the complexity of operations as much as possible while maintaining low delays and high-speed throughput. Distributed arithmetic is a powerful technique that has been used for fast and efficient implementation of 1D DCT on FPGA.