使用决策图的寄存器传输级演绎故障仿真

2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI:10.1109/BEC.2010.5631842

U. Reinsalu, J. Raik, R. Ubar

{"title":"使用决策图的寄存器传输级演绎故障仿真","authors":"U. Reinsalu, J. Raik, R. Ubar","doi":"10.1109/BEC.2010.5631842","DOIUrl":null,"url":null,"abstract":"The paper presents a deductive method for register-transfer level fault simulation on the system model of high-level decision diagrams. The method is based on the bit coverage fault model, which has been proven to have a good correspondence with gate-level structural faults. Experiments on ITC99 benchmark circuits have been carried out showing the feasibility of the proposed approach.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"354 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Register-transfer level deductive fault simulation using decision diagrams\",\"authors\":\"U. Reinsalu, J. Raik, R. Ubar\",\"doi\":\"10.1109/BEC.2010.5631842\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a deductive method for register-transfer level fault simulation on the system model of high-level decision diagrams. The method is based on the bit coverage fault model, which has been proven to have a good correspondence with gate-level structural faults. Experiments on ITC99 benchmark circuits have been carried out showing the feasibility of the proposed approach.\",\"PeriodicalId\":228594,\"journal\":{\"name\":\"2010 12th Biennial Baltic Electronics Conference\",\"volume\":\"354 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 12th Biennial Baltic Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BEC.2010.5631842\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 12th Biennial Baltic Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BEC.2010.5631842","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

本文提出了一种基于高层决策图系统模型的挂号传输级故障仿真的演绎法。该方法基于比特覆盖故障模型，该模型已被证明与门级结构故障有很好的对应关系。在ITC99基准电路上进行的实验表明了该方法的可行性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

The paper presents a deductive method for register-transfer level fault simulation on the system model of high-level decision diagrams. The method is based on the bit coverage fault model, which has been proven to have a good correspondence with gate-level structural faults. Experiments on ITC99 benchmark circuits have been carried out showing the feasibility of the proposed approach.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2010 12th Biennial Baltic Electronics Conference

自引率

0.00%

发文量