A CAD tool for custom magnitude comparators

Inarguably, the increased system complexity of modern hardware, inhibits the time-to-market of new components and jeopardizes the credibility of the design team to meet the tough time to market deadlines. In the thorny landscape of system design, EDA tools that automate the design and implementation process of various IP blocks are more than desired; they are the foundation stones of productivity. One very important class of EDA tools is the generation of hardware descriptions for popular IP blocks. One very important IP block, required in a plethora of situations, is the magnitude comparator block. Here, we present an online tool that can generate custom HDL descriptions for various bitwidths of magnitude comparator IP blocks, using only elementary gates. The generated IP blocks are vendor neutral and leverage the capabilities of the design teams that require such descriptions. Our synthesized circuits on Xilinx Virtex 6 FPGA XC6VLX760, operate up to 351 Mhz.