Design on FPGA of the IEEE 802.11p standard baseband OFDM section model

Dedicated Short-Range Communication (DSRC) technology is developed for use in vehicle-to-vehicle (V2V) and vehicle-to-roadside/infrastructure (V2I) communications. It uses Orthogonal Frequency Division Multiplexing (OFDM) as constrained by IEEE 802.11p standard. In this standard, the OFDM uses 64 sub-carriers. This paper presents the design on Field Programmable Gate Array (FPGA) Xilinx Spartan-3E of the Transmitter and Receiver Baseband OFDM Section Models for the IEEE 802.11p Stan-dard. Design is carried out using Very High speed integrated circuit hardware Description Language (VHDL). The circuits for both the Inverse Fast Fourier Transform (IFFT) and FFT processing blocks are fully combinatorial, not sequential. The results show that the resource utilization for the 64 subcarriers is more than 100 % and thus can't be realized. Therefore a smaller model with eight sub-carriers is also designed, and it is realizable (implementable).