{"title":"分析HMC原子中的一致性问题","authors":"Pranith Kumar, Lifeng Nai, Hyesoon Kim","doi":"10.1145/2989081.2989104","DOIUrl":null,"url":null,"abstract":"As 3D stacked technology gets popular, Processing-in-memory (PIM) is gaining momentum. HMC 2.0 specification offers a fine-grained, instruction granularity offloading capability to the host processor. The current work studies the potential consistency issues which arise from offloading the atomic instructions from CPU to HMC as present in the current specification.","PeriodicalId":283512,"journal":{"name":"Proceedings of the Second International Symposium on Memory Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Analyzing Consistency Issues in HMC Atomics\",\"authors\":\"Pranith Kumar, Lifeng Nai, Hyesoon Kim\",\"doi\":\"10.1145/2989081.2989104\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As 3D stacked technology gets popular, Processing-in-memory (PIM) is gaining momentum. HMC 2.0 specification offers a fine-grained, instruction granularity offloading capability to the host processor. The current work studies the potential consistency issues which arise from offloading the atomic instructions from CPU to HMC as present in the current specification.\",\"PeriodicalId\":283512,\"journal\":{\"name\":\"Proceedings of the Second International Symposium on Memory Systems\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Second International Symposium on Memory Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/2989081.2989104\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Second International Symposium on Memory Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2989081.2989104","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
As 3D stacked technology gets popular, Processing-in-memory (PIM) is gaining momentum. HMC 2.0 specification offers a fine-grained, instruction granularity offloading capability to the host processor. The current work studies the potential consistency issues which arise from offloading the atomic instructions from CPU to HMC as present in the current specification.
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