基于浮动门的CMOS阵列三维NAND技术

2015 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2015-12-01 DOI:10.1109/IEDM.2015.7409618

K. Parat, C. Dennison

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引用次数: 83

摘要

NAND闪存遵循摩尔定律已经好几代了。随着最小半间距低于20nm，需要过渡到3D NAND单元以继续缩放。本文介绍了一种基于浮栅的3D NAND技术，该技术相对于2D NAND具有优越的单元特性，并在CMOS阵列下实现高Gb/mm2密度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A floating gate based 3D NAND technology with CMOS under array

NAND Flash has followed Moore's law of scaling for several generations. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue the scaling. This paper describes a floating gate based 3D NAND technology with superior cell characteristics relative to 2D NAND, and CMOS under array for high Gb/mm2 density.

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2015 IEEE International Electron Devices Meeting (IEDM)

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