具有频闪定心结构的800MT/s多处理器总线接口

2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-11-01 DOI:10.1109/ASSCC.2006.357937

H. Muljono, S. Rusu, K. Tian, M. Atria, M. Chan, Charlie Lin

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引用次数: 0

摘要

65 nm 1.2 V GTL总线接口在3负载多处理器(MP)环境下实现了800 MT/s 6.4 GB/ s的数据速率。为了使数据速率比以前的设计提高20%，它采用了分级驱动、DLL控制的预驱动、Tco补偿、数据/频门时移器、高增益差分放大器以及先进的工艺、电压和温度(PVT)补偿设计。

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A 800MT/s Multiprocessor Bus Interface With Strobe Centering Architecture

A 65 nm 1.2 V GTL bus interface achieves 800 MT/s 6.4 GB/S data rate in a 3-load multi-processor (MP) environment. To enable a 20% increase in data rate compared to previous design, it utilizes a staged driver, DLL controlled predriver, Tco compensation, data/strobe time shifter, high gain differential amplifier as well as advanced process, voltage and temperature (PVT) compensation design.

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来源期刊

2006 IEEE Asian Solid-State Circuits Conference

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