{"title":"用于65nm CMOS软件定义无线电的0.37至46.5 ghz频率合成器","authors":"Jun Yin, H. Luong","doi":"10.1109/VLSIC.2014.6858394","DOIUrl":null,"url":null,"abstract":"Employing a switched-transformer-based triple-band Q-VCO and a magnetically-tuned multi-mode triple-push x4 injection-locked frequency multiplier (ILFM), a CMOS SDR frequency synthesizer generates IQ LO signals continuously from 0.37GHz to 23.25GHz and differential LO signals from 23.25GHz to 46.5GHz. Implemented in 65-nm CMOS, the synthesizer measures phase noise of -94dBc/Hz in band and of -136dBc/Hz at 10MHz offset from 7.2GHz and RMS jitters between 0.43ps and 0.55ps across the whole frequency range while consuming 36 to 90mW and occupying an active area of 1.82mm2.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"170 9-10","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOS\",\"authors\":\"Jun Yin, H. Luong\",\"doi\":\"10.1109/VLSIC.2014.6858394\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Employing a switched-transformer-based triple-band Q-VCO and a magnetically-tuned multi-mode triple-push x4 injection-locked frequency multiplier (ILFM), a CMOS SDR frequency synthesizer generates IQ LO signals continuously from 0.37GHz to 23.25GHz and differential LO signals from 23.25GHz to 46.5GHz. Implemented in 65-nm CMOS, the synthesizer measures phase noise of -94dBc/Hz in band and of -136dBc/Hz at 10MHz offset from 7.2GHz and RMS jitters between 0.43ps and 0.55ps across the whole frequency range while consuming 36 to 90mW and occupying an active area of 1.82mm2.\",\"PeriodicalId\":381216,\"journal\":{\"name\":\"2014 Symposium on VLSI Circuits Digest of Technical Papers\",\"volume\":\"170 9-10\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 Symposium on VLSI Circuits Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2014.6858394\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Circuits Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2014.6858394","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOS
Employing a switched-transformer-based triple-band Q-VCO and a magnetically-tuned multi-mode triple-push x4 injection-locked frequency multiplier (ILFM), a CMOS SDR frequency synthesizer generates IQ LO signals continuously from 0.37GHz to 23.25GHz and differential LO signals from 23.25GHz to 46.5GHz. Implemented in 65-nm CMOS, the synthesizer measures phase noise of -94dBc/Hz in band and of -136dBc/Hz at 10MHz offset from 7.2GHz and RMS jitters between 0.43ps and 0.55ps across the whole frequency range while consuming 36 to 90mW and occupying an active area of 1.82mm2.
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