基于降压DC-DC变换器的通用亚微米CMOS微处理器电源宏模型

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI:10.1109/ISCAS.2002.1010830

E. Kussener, H. Barthélemy, A. Malherbe, A. Kaiser

{"title":"基于降压DC-DC变换器的通用亚微米CMOS微处理器电源宏模型","authors":"E. Kussener, H. Barthélemy, A. Malherbe, A. Kaiser","doi":"10.1109/ISCAS.2002.1010830","DOIUrl":null,"url":null,"abstract":"A new SPICE macromodel that simulates a microprocessor loading impedance at the power supply is presented. This macro model has been especially created to accelerate the time to market in the design of DC-DC voltage converters used to supply submicronic digital integrated circuits. The proposed macromodel has been successfully compared to measurements for a dedicated test-chip implemented in CMOS 0.35 /spl mu/m from STM. The test-chip includes a 16 bit microprocessor supplied by a voltage down converter. SPICE simulations and measurements demonstrate the efficiency of the proposed model.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter\",\"authors\":\"E. Kussener, H. Barthélemy, A. Malherbe, A. Kaiser\",\"doi\":\"10.1109/ISCAS.2002.1010830\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new SPICE macromodel that simulates a microprocessor loading impedance at the power supply is presented. This macro model has been especially created to accelerate the time to market in the design of DC-DC voltage converters used to supply submicronic digital integrated circuits. The proposed macromodel has been successfully compared to measurements for a dedicated test-chip implemented in CMOS 0.35 /spl mu/m from STM. The test-chip includes a 16 bit microprocessor supplied by a voltage down converter. SPICE simulations and measurements demonstrate the efficiency of the proposed model.\",\"PeriodicalId\":203750,\"journal\":{\"name\":\"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2002.1010830\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2002.1010830","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

提出了一种新的SPICE宏模型，用于模拟微处理器在电源处的负载阻抗。这个宏观模型是专门为加快用于亚微米数字集成电路的DC-DC电压变换器的设计上市时间而创建的。所提出的宏模型已成功地与STM在CMOS 0.35 /spl mu/m中实现的专用测试芯片的测量结果进行了比较。测试芯片包括一个16位微处理器，由一个电压下降转换器提供。SPICE仿真和测量验证了该模型的有效性。

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Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter

A new SPICE macromodel that simulates a microprocessor loading impedance at the power supply is presented. This macro model has been especially created to accelerate the time to market in the design of DC-DC voltage converters used to supply submicronic digital integrated circuits. The proposed macromodel has been successfully compared to measurements for a dedicated test-chip implemented in CMOS 0.35 /spl mu/m from STM. The test-chip includes a 16 bit microprocessor supplied by a voltage down converter. SPICE simulations and measurements demonstrate the efficiency of the proposed model.

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来源期刊

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

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